Recent Trends and Advances in High Performance Fractional-N PLL Design
Date: Fri., Nov. 20th, 2022, 10:00 AM – 11:00 AM (MST) Alberta
Sponsored by IEEE Southern Alberta Section, Jt. CAS04/SSC37 Technical Chapter
Topic: Recent Trends and Advances in High Performance Fractional-N PLL Design
High performance fractional-N phase-locked loops (PLLs) are essential elements of any advanced electronic systems. In recent years, both analog and all-digital PLLs employing sampling or sub-sampling phase detector have gained popularity and demonstrated below 100-fs integrated jitter and superior figure-of-merit. This talk focuses on this PLL architecture and elaborates the advanced design techniques to achieve low jitter, low fractional spurs, fast locking, and low power operation. Both circuits design and digital calibration techniques will be presented in detail. In addition, recent advances in reference clock generation will also be discussed as it is crucial for high performance PLLs.