Date: Fri., Dec. 08th, 2022, 04:00 PM – 05:00 PM (MST) Alberta

Location: Virtual

Sponsored by: IEEE Southern Alberta Section, Jt. CAS04/SSC37 Technical Chapter

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Topic: Recent Trends and Advances in High Performance Fractional-N PLL Design

While SAR ADCs have become one of the most successful ADC architectures over the past decade owing to the compactness and the power-efficiency in advanced CMOS processes, pipelined ADCs seem to be somewhat out of the designer’s attention. However, we still can find some recent designs reporting competitive performances, often with SAR ADCs as their sub stage, utilizing opamp-free residue amplifiers. As high-speed single channel ADCs is preferable for time-interleaving (TI) to reduce the number of channels, the pipelined architecture is likely to remain as one of the best suited ones in achieving both high resolution and high speed. With this perspective, this talk reviews the development history of the pipelined ADCs and introduces recent architectures including the single-amp dual-residue pipelined ADC.