Date: Tue., Nov 30th, 2021, 10:00 AM to 11:30 AM (MST)

Presented by: Shuo Wei (Mike) Chen of University of Southern California (USC)

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The demand of low-power and high-speed ADC has been escalating in the past decade due to emerging low-power applications with wide bandwidth requirement, including both wireless and wireline systems. Historically, the ADC in this targeted specification regime has been dominated by Flash topology, where all the level comparisons are accomplished in parallel. However, the associated complexity prevents it from a true low-power solution. More than a decade ago, the asynchronous successive approximation (SAR) architecture was proposed to minimize the overall converter complexity while improving the speed of the SAR search algorithm. The first proof-of-concept silicon prototype in 130nm CMOS achieved the order-of-magnitude improvement in power efficiency. Since then, this low power ADC architecture has been widely adopted for various power-constraint, high-speed (up to 10s’ GS/s), medium to high resolution applications. In this talk, we will review the evolution of this ADC architecture, including the recent trend and potential extensions based on asynchronous operation principles, leading to various hybrid ADC architectures.